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Staff Engineer (Logic Pathfinding)
Samsung Semiconductor, San Jose
Phone: +1 (650)-two-seven-two-1873
E-mail: aravindhk947@gmail.com
About me
About me
I work on a CMOS technology node pathfinding - focusing on device and DTCO boosters for advanced nodes (1nm and beyond).
Expertise: device engineering, circuit modeling (parasitic modeling, ring-oscillator PPA), DTCO (standard cell architecture, block-level PPA), process integration, power-delivery circuits, and nanofabrication.
2 US patents granted, 13 U.S. patent applications filed, and over 25 peer-reviewed journal publications with 1200+ citations.
Other responsibilities: Industry Liaison for Semiconductor Research Corporation
Education
Education
PhD in Electrical Engineering, Stanford University, 2022 (Thesis), Advisor: Prof. Krishna Saraswat
Developed record-low resistance metal contacts and stable doping techniques for 2D materials like MoS₂;
MS in Electrical Engineering, Stanford University, 2018
B.Tech. (Honors) in Electrical Engineering, IIT Bombay, 2016
Minor degrees in Physics & CS
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